1. Field of the Invention
The present invention relates to art of microelectronic packaging, and more specifically to methods of encapsulating a semiconductor chip package using a pseudoplastic encapsulant having thixotropic properties.
2. Description of the Related Art
In the construction of semiconductor chip package assemblies, it has been found desirable to interpose an encapsulant between and/or around elements of the semiconductor package. An encapsulant may be used in an effort to reduce and/or redistribute the strain and stress on the connections between the semiconductor chip and the supporting circuitized substrate during operation of the chip. An encapsulant may also serve to seal the elements against corrosion, as well as to insure intimate contact between the encapsulant, the semiconductor chip and the other elements of the chip package.
Semiconductor chip packages are often encapsulated using liquid compositions that cure to form encapsulants. Such compositions frequently cure upon exposure to elevated temperatures. In order to encapsulate a semiconductor package, the liquid composition is dispensed or injected into the package. Often, a mold or fixture is placed around the package prior to dispensing the liquid composition. The mold is then placed in oven to cure the liquid composition. Once the composition is cured, the mold is removed from the oven and the package is removed from the mold. It would be desirable to remove the semiconductor chip package from the mold before curing the composition because the cure time of the composition is extended when the package is encased in the mold.
Methods of using curable liquid compositions to encapsulate semiconductor chip packages are described in, for example, commonly assigned U.S. Pat. Nos. 5,659,652; 5,766,987: U.S. patent application Ser. No. 09/067,698 filed Apr. 28, 1998; U.S. patent application Ser. No. 08/610,610, filed Mar. 7, 1997; and U.S. Pat. No. 5,776,796, the disclosures of which are incorporated herein by reference. In certain embodiments of such patents and applications, a microelectronic assembly having a semiconductor chip and a flexible, sheet-like dielectric element is disclosed. Contacts on the chip are electrically interconnected to terminals on the dielectric element. The assembly may also include a compliant layer such as an elastomer or gel disposed between the dielectric sheet and the chip to provide mechanical decoupling of the sheet and terminals from the chip. As disclosed in the aforementioned patents and patent applications, such compliant layers can be made by providing a porous layer, such as a plurality of compliant pads, between the chip and the dielectric sheet, electrically connecting the terminals to contacts on the chip and then encapsulating the resulting assembly with a curable liquid composition so that the composition penetrates into the porous layer and also covers the connections at the contacts on the chip. Upon curing, the composition forms a compliant encapsulant which becomes part of the compliant layer. In making assemblies of this nature, it is desirable to ensure that the encapsulant completely fills the porous layer, to provide a substantially void-free compliant layer in the final assembly.
Several useful methods of applying and curing the encapsulant in microelectronic assemblies have been proposed in commonly assigned, copending United States patents applications and patents. For example, as set forth in the aforementioned U.S. Pat. No. 5,766,987 patent, coverlays may be applied over the top and bottom surfaces of the assembly. Typically, several assemblies are provided in a side by side arrangement so the same top coverlay lies on the top surfaces of several assemblies. The coverlay and assembly are held in a fixture. After the space between the coverlays is brought to sub-atmospheric pressure, the fixture is tilted and the liquid encapsulant is poured into the space between the cover layers. The encapsulant is then cured while the components remain in place in the fixture.
As described in U.S. Pat. No. 5,659,952, the disclosure of which is incorporated herein by reference, and the aforementioned U.S. Pat. No. 5,776,796, the encapsulant may be applied using a nozzle or a syringe around the periphery of each subassembly. For example, as shown in the ""796 patent, a plurality of assemblies can be made using a single, unitary dielectric sheet element which incorporates the dielectric sheets of several subassemblies. The chips may be attached to the dielectric sheet and electrically connected to the terminals of the dielectric sheet. At this point, a needle connected to an encapsulant dispenser is used to trace a pattern around the peripheries of the individual chips, so that the encapsulant flows into the space between each chip and the dielectric layer. A coverlay may be used to close the bond windows in the dielectric sheet during this process. Also, during this process, the dielectric sheet typically is held in a frame. In a further variant of this process, described in U.S. patent application Ser. No. 08/975,590 filed on Nov. 20, 1997, the disclosure of which is also incorporated by reference herein, the frame and dielectric sheet are placed in a vacuum chamber, and the encapsulant dispensing operation is conducted inside the chamber, while the assembly is under vacuum. When the vacuum is released, and the chamber is brought to atmospheric or superatmospheric pressure, the pressure forces the encapsulant into the porous layer between the chip and the dielectric sheet. Further, as described in U.S. patent application Ser. No. 09/012,590, filed Jan. 23, 1998, the disclosure of which is also incorporated by reference herein, it is convenient to use a frame to hold the dielectric sheet during the assembly procedures. The frame allows for mechanical handling of the dielectric sheet without direct contact with the portions of the sheet which will be incorporated into the final assembly. For example, the compliant pads used to form the porous layer may be applied to the dielectric sheet while the dielectric sheet is mounted on the frame and the chips may be mechanically attached to the pads and electrically connected to the terminals also while the dielectric sheet is mounted on the frame.
Other methods of encapsulating an assembly are disclosed in the aforementioned Ser. No. 09/067,698 application. In certain embodiments of such application, for example, the encapsulating method includes the steps of providing a plurality of assemblies within an opening in a frame and providing top and bottom sealing layers which are sealingly connected to the frame and which extend across the opening of the frame. The top and bottom sealing layers together with the frame define an enclosed space encompassing the assemblies. The frame, sealing layers and assemblies are engaged in a fixture as, for example, by clamping the frame and sealing layers between top and bottom elements of the fixture. While the frame is engaged in the fixture a liquid encapsulant is injected into the enclosed space, between the sealing layers and around the assemblies. The encapsulant is then cured. After curing, the assemblies may be further processed before singulation or may be removed from the frame and severed from one another. While the above described inventions offer important advantages, still other improvements are desirable.
The present invention relates to a method of making a semiconductor chip package. The method of this aspect of the present invention includes the steps of attaching at least one microelectronic element, such as a semiconductor chip, to a dielectric layer; placing the dielectric layer and attached microelectronic element(s) into a mold or fixture; sealingly engaging the mold with the dielectric layer; shearing a thixotropic composition to reduce its viscosity; disposing the sheared thixotropic composition into the mold such that the area between the microelectronic element(s) and the dielectric layer is completely filled; removing the dielectric layer with the attached microelectronic element(s) and thixotropic composition from the mold; and curing the thixotropic composition to form a cured encapsulant between the microelectronic element(s) and the dielectric layer. On preferred embodiments, the sheared composition is disposed into the mold via a dispense process or an injection process.
The present invention also relates to a method of making a semiconductor chip package without using a mold. The method of this aspect of the present invention includes the steps of attaching at least one microelectronic element to a dielectric layer; shearing a thixotropic composition to reduce its viscosity; disposing the sheared composition between the microelectronic element(s) and the dielectric layer; curing the thixotropic composition to form a cured encapsulant between the microelectronic element(s) and the dielectric layer. In an alternative embodiment, the dielectric layer may be attached to a frame prior to the dispense step. In a particularly preferred embodiment, a coverlay is used in conjunction with the frame.
The present invention also relates to a method of packaging a semiconductor chip without using a mold during the curing step and without the need to use a thixotropic composition. The method of this aspect of the present invention includes the steps of attaching at least one microelectronic element to a dielectric layer; placing the dielectric layer with the attached microelectronic element(s) into a mold or fixture; sealingly engaging the mold with the dielectric layer; disposing a liquid composition to completely fill the area between the microelectronic element(s) and the dielectric layer; partially curing the liquid composition to form a cured skin on the composition; removing the dielectric layer with the partially cured composition and attached microelectronic element(s) from the mold; and vii) completing the cure of the liquid composition to form a cured encapsulant.
If a plurality of chips are disposed on the dielectric layer, then the methods of the present invention can be used to simultaneously make a plurality of semiconductor chip packages by including the step of dicing a plurality of individual semiconductor chip package from the dielectric layer after the curing step.